Analysis, Design, Simulation and Evaluation of Sigma-Delta (Σδ) Modulator for Gsm Synthesizer

Abstract

The analysis, design, simulation and evaluation of 2nd, 3rd and 4th order ΣΔ modulator and loop filter respectively are discussed, in this paper, to show their impact on the performance of fractional-N PLL-FS for GSM system. All simulation results show that the system is stable. The resulting settling time, spurious level and phase noise at 20 MHz offset frequency of this synthesizer for 2nd, 3rd and 4th order ΣΔ modulator and loop filter respectively are 2.92 µs, -35 dBc, -164 dBc/Hz, 3.28 µs, -64 dBc, -186 dBc/Hz, 3.38 µs, -79 dBc and -190 dBc/Hz for 2nd, 3rd and 4th order respectively. These results show the improvement in the spurious level and phase noise by -19 dBc, -31 dBc/Hz for 3rd order system and -34 dBc, -35 dBc/Hz for 4th order system respectively compared to the published work. CppSim program and Matlab (R2007a) are used for the simulation of ΣΔ fractional-N PLL-FS.