Chemical, Morphological and Electrical Properties of Porous Silicon Prepared by Photelectrochemical Etching

Authors

  • Ban K Mohamid Department of Applied Science, University of Technology, Baghdad-Iraq.
  • Uday M Nayef Department of Applied Science, University of Technology, Baghdad-Iraq.
  • Zena F Kadem Department of Applied Science, University of Technology, Baghdad-Iraq.

Keywords:

porous silicon, nanostructure, etching, FTIIR, AFM, electrical properties

Abstract

In this work, the nanocrystalline porous silicon (PS) films is prepared by photoelectrochemical etching of n-type silicon wafer with different currents density (20, 35 and 50 mA/cm2) and etching time 15 min on the formation nano-sized pore array with a dimension of around few hundreds nanometric. The films were characterized by the measurement of FTIR spectroscopy and atomic force microscopy properties.Chemical fictionalization during the photoelectrochemical etching show on surface chemical composition of PS. The etching possesses inhomogeneous microstructures that contain a-Si clusters (Si3–Si–H) dispersed in amorphous silica matrix and (O-SiO, C-SiO). It is observed from the FTIR analyses that the Si dangling bonds of the as-prepared PS layer have large amount of Hydrogen to form weak (Si–H) bonds. The atomic force microscopy investigation shows the rough silicon surface; with increasing etching process (current density) porous structure nucleates which leads to an increase in the width (diameter) of surface pits. Consequently, the surface roughness also increases. The electrical properties of prepared PS; namely current density-voltage characteristics under dark, show that the pass current through the PS layer decreased by increasing the current density and etching time, due to increase the resistivity of PS layer. The PS layer shows a rectifying behaviour with different rectification ratio. C-V measurements demonstrate that the behaviour of the resulting junction is more like to Schottky junction. This study makes it clear that the charge carries depletion process occur in PS layer. Moreover, the charge carries decrease and width of depletion layer increase by increasing the current density.

 

Published

2013-12-01

Issue

Section

Articles

How to Cite

[1]
“Chemical, Morphological and Electrical Properties of Porous Silicon Prepared by Photelectrochemical Etching”, ANJS, vol. 16, no. 4, pp. 145–151, Dec. 2013, Accessed: Mar. 28, 2024. [Online]. Available: https://anjs.edu.iq/index.php/anjs/article/view/546